5.8.3 [15] <5.3> Using the references from Exercise 5.3, what is the miss rate for a fully associative cache with twoword blocks and a total size of 8 words, using LRU replacement? What is the miss rate using MRU (most recently use
d) replacement? Finally what is the best possible miss rate for this cache, given any replacement policy?
Multilevel caching is an important technique to overcome the limited amount of space that a first level cache can provide while still maintaining its speed. Consider a processor with the following parameters:
