| 7.9.1 [10] <7.3> Considering the CCNUMA system described in the Exercise 7.8, assume that the system has 4 nodes, each with a singlecore CPU (each CPU has its own L1 data cache and L2 data cache). The L1 data cache is storethrough, though the L2 data cache is writeback. Assume that system has a workload where one CPU writes to an address, and the other CPUs all read that data that is written. Also assume that the address written to is initially only in memory and not in any local cache. Also, after the write, assume that the updated block is only present in the L1 cache of the core performing the write. For a system that maintains coherency using cachebased block status, describe the internode traffic that will be generated as each of the 4 cores writes to a unique address, after which each address written to is read from by each of the remaining 3 cores. | |
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